The present invention pertains to a method and apparatus for placing vias in circuit boards or the like. More particularly, the present invention pertains to the positioning of vias in adjacent layers of built-up multilayer type printed circuit boards, to allow more direct electrical connections between devices coupled to such printed circuit boards.
As is known in the art, printed circuit boards (PCBs) provide a support structure allowing the interconnection of a plurality of devices coupled to the board. For example, in a simple version of a PCB, such as a so-called xe2x80x9cFR4xe2x80x9d PCB, an epoxy resin is provided that is reinforced with woven glass fibre cloth and treated to enhance its fire retardance. Conductive material is deposited in specific areas on the PCB. Space is made available on the surface of the PCB to allow components, such as integrated circuit (IC) chips, resistors, capacitors, etc. to be inserted or otherwise electrically bonded to the surface of the PCB. The conductive material, previously deposited on the PCB, provides an electrical connection between the components as desired.
PCB technology has advanced beyond providing electrical connections in a single layer. In so-called built-up multilayer (BUM) technology, a plurality of layers of conductive connections are provided with an insulating material, such as a dielectric material disposed between each layer. Individual layers are typically coupled together conductively with vias or micro-vias and plated through holes. A via is a depression in a surface of a first layer of the built-up PCB that penetrates through the insulating layer to a conductive area disposed on a lower layer. Typically, the insulating layer is etched in a specific area down to the level of the lower layer. Then, a conductive material is deposited (e.g., sputtered) on the insulating layer and into the etched area so as to create the electrical connection between the two conductive layers.
A plated through hole (PTH) is typically a hole drilled through the substrate of the PCB where the inner surface of the PTH is coated with a conductive material. A PTH provides an electrical connection between a conductive layer on a first or front side of the substrate to a conductive layer on a second or back side of the substrate. Examples of built-up multilayer (or high density multilayer) boards are sold by Ibiden USA Corp., and under the DYCOstrate(copyright) and TWINflex(copyright) marks by WurthElektronik GmbH (Rot am See, Germany).
Referring to FIG. 1, a cross section of a built-up PCB as is known in the art is shown. PCB surface layer 11 is the top surface of substrate 10 of a built-up PCB 1. A first conductive layer 12 is placed upon an insulating layer 14, and second conductive layer 13 is placed over first conductive layer 12 with an intermediate insulating layer 15. As seen in FIG. 1, a first via 21 electrically connects first layer 12 to PCB surface layer 11, a second via 22 electrically connects second layer 13 to first layer 12.
In the built-up PCBs described above, the PTHs are typically placed at the same distance away from one another. Thus, the term xe2x80x9cPTH pitchxe2x80x9d refers to the distance between corresponding points of two adjacent PTHs. In FIG. 1, the PTH pitch is set to 40 to 50 mils (where one mil equals one thousandth of an inch). It is accepted practice that a via on a first layer of a built-up PCB cannot be placed directly over a via in an adjacent layer. This is because doing so would electrically connect three adjacent layers in the PCB. Another accepted practice is that a via cannot be placed over a PTH. This is because of an assumed danger that doing so may cause one or more layers to collapse into the PTH. This practice is changing, however, and vias are now being placed over PTHs in the second or higher layer over the PTH.
Given the above limitations, the typical xe2x80x9cvia pitchxe2x80x9d (distance between the center points of adjacent vias on a given layer) is typically set to twice the PTH pitch (e.g., 80 to 100 mils). Referring to FIG. 1, the optimal placement for via 22 is midway between vias 21 and 23 as further described below. If it is assumed that an IC circuit 30 (e.g., a controlled collapse chip connection (CCCC) mounted processor such as a Pentium(copyright) processor) is placed on a bottom side of PCB substrate 10, it is known in the art to provide a decoupling capacitor 25 electrically coupled to the IC circuit chip via PCB 1. Current travels from the IC chip through plated through hole 31 to capacitor 25 through vias 21 and 22. Given a via pitch that is twice the PTH pitch, the placement of via 22 midway between vias 21 and 23 provides the shortest current path between IC chip 30 and capacitor 25. In this example, the current path includes one-half of the PTH pitch (in layer 11) and one-half of the via pitch (in layer 12).
There are at least two problems that can occur with using the via system shown in FIG. 1. The first is an appreciable amount of so-called parasitic inductance and resistance that exists between IC chip 30 and capacitor 25. This is due in part to the length of the current path from IC chip 30 and capacitor 25 caused by the via pitch. The second problem pertains to a structure referred to as a power grid. Referring to FIG. 2, a top view of a built-up board is shown as is known in the art. Large conductive pads 40a, b, c are provided in the uppermost layer of the board and are coupled to a voltage supply or ground. When placing vias (e.g., vias 41a, b, c) in this uppermost layer, it is a general requirement that the via be placed completely within the large pads 40a, b, c so as to form a better electrical connection with the layer underneath this uppermost layer. Also, as stated above, the via is generally not to be placed above a PTH (e.g., PTH 42) which can typically reside directly below one of the pads 40a, b, c in the PCB substrate. Placing such vias in precise locations presents difficulties to the PCB manufacturer.
In view of the foregoing problems in built-up board technology, there is a need for an improved method and apparatus to electrically couple adjacent layers in a built-up PCB.
According to an embodiment of the present invention, an apparatus is provided to electrically couple a conductive layer to a conductive element. A first insulating layer is disposed below a first, upper conductive layer, and a conductive element is disposed below the first insulating layer. An elongated via in the first conductive layer and first insulating layer has a length sufficient to electrically couple the first conductive layer to the conductive element through the first insulating layer.